High-Yield Fabrication of Large-Format Substrates with Distributed, Independent Control Elements

ABSTRACT

A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s).

CLAIM OF PRIORITY

This application is a continuation of U.S. patent application Ser. No.13/395,813 filed on May 25, 2012 which application is a 35 U.S.C. §371national phase application of PCT International Application No.PCT/US2010/002519, entitled “High-Yield Fabrication Of Large-FormatSubstrates With Distributed, Independent Control Elements”, having aninternational filing date of Sep. 16, 2010, which claims priority fromU.S. Provisional Patent Application No. 61/242,955, filed on Sep. 16,2009, in the United States Patent and Trademark Office, the disclosuresof which are incorporated by reference herein in their entireties. Theabove PCT International Application was published in the Englishlanguage and has International Publication No. WO 2011/034586 A2.

FIELD OF THE INVENTION

The present invention relates to large-format substrates withdistributed, independent control elements and, in particular, to methodsfor fabricating such substrates with a high yield.

BACKGROUND OF THE INVENTION

Flat-panel display devices are widely used in conjunction with computingdevices, in portable devices, and for entertainment devices such astelevisions. Such displays typically employ a plurality of pixelsdistributed over a substrate to display images. Display devices aretypically controlled with either a passive-matrix control employingelectronic circuitry external to the substrate or an active-matrixcontrol employing electronic circuitry formed directly on the substrate.Organic Light-Emitting Diode (OLED) display devices have been fabricatedwith active-matrix (AM) driving circuitry in order to produce highperformance displays. An example of such an AM OLED display device isdisclosed in U.S. Pat. No. 5,550,066. Active-matrix circuitry iscommonly achieved by forming thin-film transistors (TFTs) over asubstrate and employing a separate circuit to control eachlight-emitting pixel in the display.

In an active-matrix device, active control elements comprise thin-filmsof semiconductor material formed over a substrate, for example amorphousor poly-crystalline silicon, and distributed over a flat-panel displaysubstrate. Typically, each display sub-pixel is controlled by onecontrol element, and each control element includes at least onetransistor. For example, in a simple active-matrix organiclight-emitting (PLED) display, each control element includes twotransistors (a select transistor and a power transistor) and onecapacitor for storing a charge specifying the luminance of thesub-pixel. Each light-emitting element typically employs an independentcontrol electrode and a common electrode. Control of the light-emittingelements is typically provided through a data signal line, a selectsignal line, a power connection and a ground connection. Active-matrixelements are not necessarily limited to displays and can be distributedover a substrate and employed in other applications requiring spatiallydistributed control.

The TFTs of an active-matrix display device may be composed of a thinlayer (usually 100-400 nm) of a semiconductor such as amorphous siliconor polysilicon. The properties of such thin-film semiconductors are,however, often not sufficient for constructing a high-quality display.Amorphous silicon, for example, may be unstable in that its thresholdvoltage (Vth) and carrier mobility may shift over extended periods ofuse. Polysilicon often has a large degree of variability across thesubstrate in threshold voltage (Vth) and carrier mobility due to thecrystallization process. Since OLED devices operate by currentinjection, variability in the TFTs can result in variability of theluminance of the OLED pixels and degrade the visual quality of thedisplay. Compensation schemes, such as adding additional TFT circuitryin each pixel, have been proposed to compensate for TFT variability;however, such compensation may add complexity, which can negativelyimpact yield, cost, and/or reduce the OLED emission area. Furthermore,as thin-film transistor fabrication processes are applied to largersubstrates, such as are often used for large flat-panel televisionapplications, the variability and process cost may increase.

One approach to avoiding these issues with thin-film transistors isinstead to fabricate conventional transistors in a semiconductorsubstrate and then transfer these transistors onto a display substrate.U.S. Patent Application Publication No. 2006/0055864 A1 by Matsumura etal. teaches a method for the assembly of a display using semiconductorintegrated circuits (ICs) affixed within the display for controllingpixel elements, where the embedded transistors in the ICs replace thenormal functions performed by the TFTs of prior-art displays. Matsumurateaches that the semiconductor substrate should be thinned, for exampleby polishing, to a thickness of between 20 micrometers to 100micrometers. The substrate is then diced into smaller pieces containingthe integrated circuits, hereafter referred to as ‘chiplets’. Matsumurateaches a method of cutting the semiconductor substrate, for example byetching, sandblasting, laser-beam machining, or dicing. Matsumura alsoteaches a pick-up method where the chiplets are selectively picked upusing a vacuum chuck system with vacuum holes corresponding to a desiredpitch. The chiplets are then transferred to a display substrate wherethey are embedded in a thick thermoplastic resin.

The process taught by Matsumura, however, may have severaldisadvantages. For example, semiconductor substrates are typically 500micrometers to 700 micrometers in thickness; therefore, thinning thesubstrate in this fashion may be difficult and, at low thicknesses, thecrystalline substrate may be very fragile and may be easily broken.Therefore the chiplets may be very thick, at least 20 micrometersaccording to Matsumura. The thick chiplets of Matsumura may result insubstantial topography across the substrate, which may make thesubsequent deposition and patterning of metal layers over the chipletsmore difficult. For example, Matsumura describes concave deformations asone undesirable effect.

Another disadvantage of the process taught by Matsumura is that thesurface area of the chiplets must typically be large enough to be pickedup by the vacuum-hole fixture. As a result, the chiplets may have alength and a width that are larger than the minimum size of the vacuumhole.

Employing an alternative control technique, Matsumura et al. describecrystalline silicon substrates used for driving LCD displays in U.S.Patent Application 2006/0055864. This application describes a method forselectively transferring and affixing pixel-control devices made fromfirst semiconductor substrates onto a second planar display substrate.Wiring interconnections within the pixel-control device and connectionsfrom busses and control electrodes to the pixel-control device areshown.

In either of the above methods, there is a chance that chipletsdeposited on a substrate may be misplaced, that the chiplets may befaulty, and/or that the chiplets may fail to be placed entirely.Moreover, subsequent substrate processing steps can damage the chiplets,inadvertently relocate the chiplets, and/or fail to interconnectchiplets properly. Such process failures can render the substratecompletely or partially inoperable.

SUMMARY OF THE INVENTION

Some embodiments of the invention pertain to methods of makinglarge-format substrate with distributed control elements. The methodcomprises:

-   -   a) providing a substrate and a wafer, the wafer having a        plurality of separate, independent chiplets formed thereon; then    -   b) imaging the wafer and analyzing the wafer image to determine        which of the chiplets are defective; then    -   c) removing the defective chiplet(s) from the wafer leaving        remaining chiplets in place on the wafer; then    -   d) printing the remaining chiplet(s) onto the substrate forming        empty chiplet location(s); and then    -   e) printing missing chiplet(s) from the same or a different        wafer into the empty chiplet location(s).

According to further embodiments of the present invention, a method offabricating integrated circuit elements on a receiving substrateincludes providing a wafer having a plurality of chiplets thereon;determining that at least one of the chiplets on the wafer is defective;selectively removing the at least one of the chiplets from the waferleaving remaining ones of the chiplets on the wafer; transferring theremaining ones of the chiplets from the wafer onto the receivingsubstrate to define at least one empty chiplet location on the receivingsubstrate; and transferring at least one additional chiplet onto to theat least one empty chiplet location on the receiving substrate.

In some embodiments, determining that the at least one of the chipletsis defective may include imaging the wafer to provide a wafer image andanalyzing the wafer image to determine that the at least one of thechiplets is defective, and/or electrically testing the plurality ofchiplets on the wafer to determine that the at least one of the chipletsis defective.

In some embodiments, the wafer may be a source wafer on which theplurality of chiplets were fabricated. The at least one additionalchiplet may be transferred onto the at least one empty chiplet locationon the receiving substrate from the source wafer, or from a differentwafer.

In some embodiments, transferring the remaining ones of the chipletsonto the receiving substrate may include printing the remaining ones ofthe chiplets onto the receiving substrate in parallel.

In some embodiments, the receiving substrate may be imaged aftertransferring the remaining ones of the chiplets thereon to provide asubstrate image, and the substrate image may be analyzed to determinethe at least one empty chiplet location.

In some embodiments, the receiving substrate may be imaged aftertransferring the remaining ones of the chiplets or after transferringthe at least one additional chiplet thereon to provide a substrateimage, and the substrate image may be analyzed to identify that at leastone of the chiplets on the receiving substrate is mis-located ordefective.

In some embodiments, the receiving substrate may include an adhesivelayer thereon. The at least one of the chiplets identified asmis-located or defective may be selectively removed from the receivingsubstrate before curing of the adhesive layer.

In some embodiments, the at least one of the chiplets identified asmis-located or defective may be selectively removed by providing avacuum element operable to adhere the at least one of the chipletsidentified as mis-located or defective by air pressure, and mechanicallyremoving the at least one of the chiplets identified as mis-located ordefective using the vacuum element.

In some embodiments, the at least one of the chiplets identified asmis-located or defective may be selectively removed by providing agripping element operable to grip and mechanically remove the at leastone of the chiplets identified as mis-located or defective, andmechanically removing the at least one of the chiplets identified asmis-located or defective using the gripping element.

In some embodiments, electrical connections may be formed to theremaining ones of the chiplets and the at least one additional chipleton the receiving substrate to define a plurality of interconnectedchiplets on the receiving substrate. It may be determined that at leastone of the interconnected chiplets has a fault therein.

In some embodiments, determining that at least one of the interconnectedchiplets includes the fault may include imaging the receiving substrateto provide a substrate image and analyzing the substrate image todetermine that the at least one of the interconnected chiplets has thefault, and/or electrically testing the plurality of interconnectedchiplets to determine that the at least one of the interconnectedchiplets has the fault.

In some embodiments, the at least one of the interconnected chipletshaving the fault therein may be selectively removed from the receivingsubstrate to define at least one second empty chiplet location on thereceiving substrate.

In some embodiments, selectively removing the at least one of theinterconnected chiplets having the fault therein may include removingmaterial adhered to and surrounding the at least one of theinterconnected chiplets having the fault therein, and then selectivelyremoving the at least one of the interconnected chiplets having thefault therein. For example, the material adhered to and surrounding theat least one of the interconnected chiplets having the fault therein maybe removed by laser ablation or by local chemical processing.

In some embodiments, the local chemical processing may be aphotolithographic process, and the material may be removed by coating aphotosensitive resin over the receiving substrate, and pattern-wiseexposing and processing the photosensitive resin to form a locallychemically processable area over and around the at least one of theinterconnected chiplets having the fault therein.

In some embodiments, at least one second chiplet may be printed into theat least one second empty chiplet location on the receiving substrate,and electrical interconnections may be formed to the at least one secondchiplet.

In some embodiments, a second chiplet may be printed on the at least oneof the interconnected chiplets having the fault therein on the receivingsubstrate, and electrical interconnections may be formed to the secondchiplet. For example, an adhesive layer and/or a planarization layer maybe provided on the at least one of the interconnected chiplets havingthe fault therein before printing the second chiplet thereon.

In some embodiments, the at least one of the chiplets that wasselectively removed from the wafer may be printed onto a differentadhesive substrate.

In some embodiments, a photosensitive adhesive layer may be provided onthe receiving substrate prior to transferring the remaining ones of thechiplets to the receiving substrate; and

the adhesive layer may be selectively exposed at locations of the atleast one of the chiplets identified as mis-located or defective toreduce adhesion between the receiving substrate and the at least one ofthe chiplets identified as mis-located or defective.

In some embodiments, the wafer may include a buried oxide layer havingthe plurality of chiplets thereon. A release etch of portions of theburied oxide layer may be performed to separate portions of the chipletsfrom the wafer prior to selectively removing the at least one of thechiplets determined to be defective.

In some embodiments, an OLED device may be formed on the receivingsubstrate. The OLED device may be configured to be controlled by thechiplets on the receiving substrate.

Other methods and/or devices according to some embodiments will becomeapparent to one with skill in the art upon review of the followingdrawings and detailed description. It is intended that all suchadditional embodiments, in addition to any and all combinations of theabove embodiments, be included within this description, be within thescope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view of four pixels of an OLED display;

FIG. 2A is a cross-sectional view along line X-X′ of the device of FIG.1 in a pixel without a color filter;

FIG. 2B is a cross-sectional view along line U-U′ of the device of FIG.1 in a pixel where a color filter is used;

FIG. 3A is a circuit schematic of the integrated circuit chiplet;

FIG. 3B is a circuit schematic of the integrated circuit chiplet;

FIG. 4 is a flowchart illustrating a process for forming a OLED displaywith chiplet driving circuitry;

FIG. 5 shows a partial layout view of a wafer containing chiplets priorto picking up the chiplets;

FIGS. 6A and 6B are cross sectional views along lines Y-Y′ and Z-Z′ ofFIG. 5, respectively;

FIG. 7 is a detailed cross-sectional view of a chiplet;

FIG. 8 is a plan view of the stamp used to pick up and transfer thechiplets;

FIG. 9 is a plan view of the chiplet stamp over the chiplets on thesemiconductor substrate;

FIG. 10 shows an electrostatic damage prevention circuit diagram; and

FIG. 11 is a flowchart illustrating an embodiment of a method accordingto the present invention.

The drawings described above in accordance with embodiments of thepresent invention are necessarily of a schematic nature, since layerthickness dimensions can be in the sub-micrometer ranges, while featuresrepresenting lateral device dimensions can be in a range from 10micrometers to a meter or more. Accordingly, the drawings are scaled forease of visualization rather than for dimensional accuracy.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can therefore, encompasses both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

The terminology used in the description of the invention herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the invention. As used in the description ofthe invention and the appended claims, the singular forms “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will also be understood that theterm “and/or” as used herein refers to and encompasses any and allpossible combinations of one or more of the associated listed items. Itwill be further understood that the terms “comprises” and/or“comprising,” when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

Unless otherwise defined, all terms used in disclosing embodiments ofthe invention, including technical and scientific terms, have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs, and are not necessarily limited to thespecific definitions known at the time of the present invention beingdescribed. Accordingly, these terms can include equivalent terms thatare created after such time. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe present specification and in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. All publications, patent applications,patents, and other references mentioned herein are incorporated byreference in their entireties.

Reference is made herein to commonly assigned, co-pending U.S.application Ser. No. (EK Docket 94848) and to U.S. patent applicationSer. No. 11/145,574, the disclosures of which are incorporated byreference herein as if set forth in their entireties.

The present invention is directed to manufacturing methods forconstructing a large-format substrates (generally referred to herein asreceiving substrates) having multiple, independent control elements(also referred to herein as chiplets), where each control elementincludes a respective substrate that is separate and independent fromthe large-format substrate. In some embodiments,

it may be desirable that the chiplets have a thickness of less than 20micrometers, and preferably less than 10 micrometers. Such thinnerchiplets may reduce topography problems and facilitate formation ofsubsequent layers above the chiplets. It may also be desirable toinclude multiple metal wiring layers in the chiplet, and thus, thethickness of the semiconductor portion of the chiplet may besubstantially thinner than the total thickness of the chiplet.

A general description of devices for controlling an OLED displayaccording to some embodiments is first provided. In some embodiments, itmay be desirable that the surface area of each chiplet is small enoughto enable high-resolution displays and so that many chiplets can beproduced on a single substrate, thereby enabling a low unit productioncost. It may also be desirable that the shape of the chiplet be made tofit between pixels and not block light emission. Therefore, the chipletmay have a length or width that is narrow compared to the otherdimension so that it can be placed in the spacing between the rows orthe columns of pixels. After the device is described, methods accordingto some embodiments of the present invention are described.

FIG. 1 shows a layout view of a group of four pixel elements (20 a, 20b, 20 c and 20 d) of an OLED display device. Each of the four pixels canbe arranged to emit light of a different color, such as red, green, blueand white (RGBW) light. FIG. 1 represents a portion of a full display,where the full display would be constructed of an array of such groupsof pixels arranged in many rows and columns. For example, a moderntelevision would be constructed having 1920 rows and 1080 columns ofsuch groups of pixels.

A chiplet 120 is arranged to control the electrical current to pixels 20a, 20 b, 20 c and 20 d. A chiplet is a separately fabricated integratedcircuit element that is mounted and embedded into the display device.Much like a conventional microchip (or chip), a chiplet is fabricatedfrom a substrate and contains integrated transistors as well asinsulator layers and conductor layers that are deposited and thenpatterned, for example, using photolithographic methods in asemiconductor fabrication facility (or fab). These transistors in thechiplet are arranged in a transistor drive circuit, as will be describedin greater detail below, to drive the electrical current to pixels ofthe display.

A chiplet is smaller than a traditional microchip. Unlike traditionalmicrochips, electrical connections may not be made to a chiplet by wirebonding or flip-chip bonding. Instead, after arranging and mounting eachchiplet onto a receiving substrate, such as the display substratesdescribed herein, deposition and photolithographic patterning ofconductive layers and insulator layers continues on the receivingsubstrate. Therefore, the connections can be made relatively small, forexample through using vias of about 2 to about 15 micrometers in size.The chiplet and connections to the chiplet are small enough to be placedwithin the area of one or more pixels which, depending on the displaysize and resolution, may range from approximately 50 micrometers to 500micrometers in size. Additional details about such chiplets and relatedfabrication and mounting processes will be described below.

Alignment marks 130 a and 130 b are provided on the display substrate100 (called out in FIG. 2A). Preferably, to avoid reduction of the pixelemission area, these alignment marks 130 a, 130 b may be located underthe display signal lines. Each of the pixels 20 a, 20 b, 20 c, 20 d isprovided with a lower electrode, such as a lower electrode 161 a inpixel 20 a. The emitting area of pixel 20 a is defined by an opening 163a in an insulator formed over the lower electrode. Multiple conductiveelements may be formed in a first conductive layer, and may be arrangedto facilitate providing electrical signals to the chiplet's transistordrive circuitry to enable the chiplet to control electrical current tothe pixels. Chiplet 120 controls current to pixel 20 a through aconductor 133 a. For example, conductor 133 a is connected to chiplet120 through a via 143 a and is also connected to lower electrode 161 athrough a via 153 a.

The display device also includes a series of signal lines including,power lines, data lines, and select lines which are formed in the firstconductive layer and transmit electrical signals from the edge of thedisplay to the chiplets. Power lines are signal lines that provide asource of electrical current to operate the organic electroluminescentelements. Data lines are signal lines that transmit luminanceinformation to regulate the luminance of each pixel. Select lines arelines that selectively determine which rows of the display are toreceive luminance information from the data lines. As such, select linesand data lines may be routed in an orthogonal manner.

Power is provided to the chiplet 120 by way of a power line 131. Twovias are provided for connection between the power line and the chiplet120. A data line 135 is provided in the column direction forcommunicating a data signal containing luminance information to chiplet120 for pixel 20 a and pixel 20 c. Similarly, a data line 136 isprovided in the column direction for communicating a data signalcontaining luminance information to chiplet 120 for pixel 20 b and pixel20 d. In other embodiments, discussed in greater detail below, the datalines 135 and 136 and the power line 131 may be connected to the chiplet120 by only a single via for each line. A select line segment 137 a isprovided in the row direction for communicating a row select signal tochiplet 120 for pixel 20 a and pixel 20 b. The row select signal is usedto indicate a particular row of pixels and is synchronized with the datasignal for providing luminance information. Thus the row select signaland the data signals are provided in orthogonal directions. Chiplet 120communicates the row select signal from select line segment 137 a to aselect line segment 137 b by way of an internal pass-thru connection onthe integrated circuit. Select line segment 137 b then communicates therow select signal to subsequent chiplets arranged in the same row.Similarly a select line segment 138 a is provided in the row directionfor communicating a row select signal to chiplet 120 for pixel 20 c andpixel 20 d. Chiplet 120 communicates the row select signal from selectline segment 138 a to a select line segment 138 b by way of anotherinternal pass-thru connection on the integrated circuit. Select linesegments 137 a and 137 b together serve to form a single select line,which is physically discontinuous but electrically continuous. Aconnection between the select line segments is provided by the pass-thruconnections in the chiplet. While only two segments are shown, theselect line can contain a series of many such segments. Select linesegments 138 a and 138 b similarly together serve to form a singlephysically discontinuous but electrically continuous select line. Insome embodiments of the present invention, all of the select linessegments and data lines may be formed from a single metal layer.Communication across the orthogonal array may be achieved by routing therow select signal, the data signal, or both through the pass-thruconnections on the chiplet.

FIG. 2A shows a cross sectional view of the OLED display device of FIG.1 taken along line X-X′, where pixel 20 a is a white pixel, and thusdoes not include a color filter. The display device is constructed overa display substrate 100. Alignment marks 130 are defined on the displaysubstrate 100. One approach for defining these alignment marks is tophoto-lithographically define patterns in a metal layer having athickness of less than about 100 nm. Over the display substrate 100, anadhesive layer 111 is provided. One material that may be used foradhesive layer 111 is Benzocyclobutene (BCB), which may be formed byspin coating to thickness of approximately 0.5 to approximately 10micrometers. Chiplet 120 is placed on the adhesive layer 111. Thechiplet has a thickness (H) that is may be less than about 20micrometers and, in some embodiments, less than about 10 micrometers.Planarization layer 112 is provided to reduce the topography aroundchiplet 120 and facilitate continuous formation of a subsequentconductive layer. A planarization layer 112 may be formed at a thicknessgreater than the thickness (H) of the chiplet 120. A material that maybe used for planarization layer 112 is Benzocyclobutene (BCB) formed byspin coating. It may be advantageous to use the same material for theadhesion layer 111 and the planarization layer 112 in some embodimentsso as to reduce differences in refractive index that can cause opticalreflections at the interface of these two layers. Therefore by using thesame material, the refractive index of the adhesion layer 111 and theplanarization layer 112 layers may be the same.

Via 143 a is opened in the planarization layer 112 and an optionalinsulator sub-layer 121 on chiplet 120 to provide access to a connectionpad 353 a. Formation of this via can be done using photolithographytechniques and is facilitated if a photo-imagable BCB compound is usedfor planarization layer 112. Chiplet 120 is mounted over substrate 100such that the connection pads, such as connection pad 353 a, are facingupward. The arrangement may be referred to as a “pad-up” configuration.In particular, the transistor circuitry in the chiplet (not shown) isdisposed between the connection pads and the substrate 100. Thisarrangement may be advantageous in that it provides convenient access tothe connection pads for subsequent wiring layers.

Over planarization layer 112, a conductor layer (or wiring layer) isformed. This conductor layer may be patterned using conventionalphotolithography techniques into the select lines, data lines, and powerlines, as well as the connectors between the chiplets and the anodes,such as conductor 133 a. Electrical connection between the conductorlayer and the chiplet 120 can then be readily made through vias, such asvia 143 a. This enables high quality, reliable electrical connectivity.Since the current to the pixels is provided by the wiring layer, thislayer may be constructed to have low resistance. In this regard,materials for the wiring layer may include aluminum or aluminum alloysformed to a thickness of approximately 200 to approximately 500 nm.

Over this wiring layer, an insulator layer 113 is formed. Vias, such asvia 153 a, provide for connection to the wiring layer from above. Lowerelectrode 161 a is provided over insulator layer 113. In this bottomemitter configuration, lower electrode 161 a is formed to be at leastpartially transparent. Materials that may be used for the lowerelectrode 161 include transparent conductive oxides such as Indium TinOxide (ITO) or Aluminum doped Zinc Oxide (AZO) or the like. Thin metalssuch as less than about 25 nm of aluminum, silver, or the like can alsobe used. Over the edges of lower electrode 161 a, an insulator layer 114is formed. This insulator layer 114 can be constructed, for example, ofa photo-patterned polymer and serves to prevent high electric fields atthe edges of the lower electrode 161 a. Similar insulator layers forthis purpose are described in U.S. Pat. No. 6,246,179. Opening 163 a isprovided in the insulator layer to provide for contact to the lowerelectrode 161 a.

Above lower electrode 161 a, an organic electro-luminescent medium 165is formed. There are many such different organic electro-luminescentmedia configurations known in the art. Although the organicelectro-luminescent medium 165 is shown as a single layer, it mayinclude a plurality of sub-layers such as a hole transporting sub-layerand an electron transporting sub-layer. Organic electro-luminescentmedium 165 can include additional sub-layers such as hole injectingsub-layers, electron injecting sub-layers, and/or specialized lightemitting sub-layers. For the organic electro-luminescent media 165, abroadband (or white) light source which emits light at variouswavelengths used by all of the differently colored pixels may be used insome embodiments to avoid the need for patterning the organicelectro-luminescent media between light producing units. Colored pixelsmay be achieved by aligning color filter elements with light producingelements. Some examples of organic electro-luminescent (EL) media layersthat emit broadband or white light are described, for example, in U.S.Pat. No. 6,696,177. However, embodiments of the present invention canalso be made to work where each pixel has one or more of the organicelectro-luminescent media sub-layers separately patterned for eachpixel. The organic EL media may be constructed of several sub-layerssuch as; a hole injecting sub-layer, a hole transporting sub-layer thatis disposed over the hole injecting sub-layer, a light-emittingsub-layer disposed over the hole transporting sub-layer, and an electrontransporting sub-layer disposed over the light-emitting sub-layer.Alternate constructions of the organic electro-luminescent media 165having fewer or more sub-layers can also be used in some embodiments ofthe present invention.

Over organic electro-luminescent medium 165, an upper electrode 169 isformed. Although shown as a single layer, upper electrode 169 can alsoinclude a plurality of sub-layers. Several upper-electrodeconfigurations are known in the art. For example, the upper electrode169 may include a sub-layer of Li or LiF approximately 0.5 nm thick incontact with the organic electro-luminescent medium 165 for facilitatingelectron injection followed by a sub-layer of Al approximately 100 toapproximately 400 nm thick. Other features such as a moisture barrierencapsulation (not shown) or desiccant (not shown) used in the art offabricating OLED devices can also be included. Current flow between thelower electrode 161 a and the upper electrode 169 through the organicelectro-luminescent medium 165 results in light emission 50.

FIG. 2B shows a cross-sectional view of the OLED display device of FIG.1 along line U-U′, where pixel 20 b has a color filter. The color filter190 a is placed under the light emitting area, and can be depositedbefore the adhesive layer 111 as shown. In other embodiments, the colorfilter can be placed on top of the adhesive. For an RGBW type display,the white pixels can be constructed without color filters. Color filterscan be formed by methods such as spin coating and are approximately 1 toapproximately 3 micrometers in thickness. In some embodiments, the colorfilter may be placed under the planarization layer 112 so that theplanarization layer serves to planarize both the color filters and thechiplet 120. The color filters may be formed prior to mounting thechiplets. Since the chiplets are relatively thick, their presence canimpair proper spin coating of the color filters, so that deviceperformance and yield are enhanced by stamping the chiplets afterforming the color filters. Furthermore, the color filter process can beinspected and defective devices discarded prior to placing the chipletsso as to reduce the chance of wasting chiplets, thereby reducing overallproduction cost.

FIG. 3A illustrates a schematic drawing of an integrated circuit 300provided on each chiplet according to embodiments of the presentinvention. Integrated circuit 300 is arranged to drive four independentOLED pixel elements. Integrated circuit 300 includes four selecttransistors (320 a, 320 b, 320 c and 320 d), four storage capacitors(330 a, 330 b, 330 c and 330 d) and four drive transistors (340 a, 340b, 340 c and 340 d). Other circuits with more or fewer components canalso be employed. These components are connected to several connectionpads arranged in two rows including connection pads 351 a, 351 b, 353 a,353 b, 354 a, 355 a and 356 a arranged in a first row and connectionpads 352 a, 352 b, 353 c, 353 d, 354 b, 355 b and 356 b arranged in asecond row. Connection pads 353 a, 353 b, 353 c and 353 d are providedfor connection to the lower electrode (anode) of the organic lightemitting diode element of each pixel. These connection pads areelectrically connected to drive transistors 340 a, 340 b, 340 c and 340d respectively. Connection pads 356 a and 356 b are arranged forconnection to an external power supply line, are electrically connectedby pass-thru connection 316 and are electrically connected to all of thedrive transistors 340 a, 340 b, 340 c and 340 d. Connection pads 351 aand 351 b are arranged for connection to a first external select line,are electrically connected by a pass-thru connection 311 a and areelectrically connected to the gates of select transistors 320 a and 320b. Connection pads 352 a and 352 b are arranged for connection to asecond external select line, are electrically connected by pass-thruconnection 311 b and are electrically connected to the gates of toselect transistors 320 c and 320 d. Connection pads 354 a and 354 b arearranged for connection to a first external data line, are electricallyconnected by a pass-thru connection 314 a and are electrically connectedto select transistors 320 a and 320 c. Connection pads 355 a and 355 bare arranged for connection to a first external data line, areelectrically connected a by pass-thru connection 314 b and areelectrically connected to select transistors 320 b and 320 d.

In order for the external select lines to address the rows of pixels ofthe display and the external data lines to address the columns of thedisplay, these lines may be arranged in an orthogonal pattern. It may bedesirable that these external lines be formed from a single metal layerto avoid additional manufacturing steps. This may be achieved by routingeither the data signal or the select signal through the pass-thruconnections on the chiplet. In the case shown, the select signals, thedata signals, and the power signal are all provided with pass-thruconnections. The external select lines are discontinuous and require thepass-thru connections to complete the connection. The external datalines and power lines, however, are continuous. In this case, providingtwo connection pads with a pass-thru connection for each of the two datasignals and power signals has an advantage of redundancy. That is, ifone of the connections between the connection pad and the external datalines or the external power lines is not fully formed or is otherwiseincomplete, the device will continue to function.

In other embodiments of the present invention, pass-thru connections canbe provided for only the select signal and not the data signal or viceversa. The pass-thru connection for the power signal can also beoptionally eliminated. In addition to removing the pass-thruconnections, one of the two connection pads associated with each of theremoved pass-thru connections can also be removed. One such alternateembodiment is shown in FIG. 3B. The embodiment of FIG. 3B provides anadvantage that surface area of the chiplet needed for circuitry andconnection pads may be reduced. However, this alternate embodiment maynot offer the advantage of redundant connections for the data signal andpower signal.

FIG. 1 to FIG. 3B show embodiments where the chiplet drives four pixels,and where the four pixels respectively emit red, green, blue, and whitelight. In an other embodiments, the chiplet could drive a differentnumber of pixels, for example eight, twelve or sixteen pixels. Forexample, a chiplet controlling sixteen pixels including 4 red, 4 green,4 blue and 4 white sub-pixels can be constructed. The chiplet may drivean equal number of each different color sub-pixels, such as N redsub-pixels, M green sub-pixels, P blue sub-pixels, and Q whitesub-pixels where N=M=P=Q, and where N is an integer equal to 2 or more.Since each differently colored pixel can require different drivingcurrents due to different color efficiencies, the transistor design(such as the channel ratio of the channel width to channel length) canbe separately improved or optimized for each different color. Thus thereis an advantage in display designs where each chiplet drives an equalnumber of pixels of each color such that all chiplets can be made thesame. Such arrangements also facilitate the placing of the chipletssymmetrically within the display area.

FIG. 4 is a block diagram describing the process steps for making anOLED display. The process 500 begins with step 510 by forming integratedcircuit elements. These integrated circuit elements are arranged in aconfiguration to drive one or more pixels of the OLED display. Theintegrated circuit elements may be formed from a silicon-on-insulatortype (SOI) substrate using known integrated circuit fabricationtechniques. SOI substrates include a crystalline silicon layer formedover an insulator layer, such as silicon dioxide, which is in turnformed over a bulk crystalline silicon wafer. The silicon dioxide layeris commonly referred to as the “buried oxide” or “BOx”. SOI wafers maybe fabricated by bonding a first silicon wafer with a silicon dioxidelayer to a second silicon wafer, followed by cleaving or thinning thesecond silicon wafer such that a thin film of crystalline siliconremains over the silicon dioxide layer. Such SOI wafers are commerciallyavailable from a variety of suppliers. A substrate used for forming theintegrated circuit for the chiplets may generally be referred to as an“integrated circuit substrate”.

In step 520, a release etch is performed to partially separate thechiplets from the integrated circuit substrate. This step is furtherillustrated in the layout view of the chiplet partially attached to theintegrated circuit substrate shown in FIG. 5 and in cross sectionalviews of FIG. 6A and FIG. 6B. FIG. 6A is a cross sectional view fromFIG. 5 taken along line Y-Y′ and FIG. 6B is a cross sectional view fromFIG. 5 taken along line Z-Z′. Chiplet 120 is formed from an integratedcircuit substrate which is of the silicon on insulator type. The siliconon insulator substrate consists of a semiconductor layer 605, which maybe less than about 10 micrometers in thickness and, in some embodiments,between about 0.05 and about 5 micrometers in thickness, separated froman integrated circuit substrate bulk 601 by a buried oxide with athickness of between about 0.1 to about 3.0 micrometers. In the area ofthe chiplet, the semiconductor layer 605 contains the semiconductorportions, including doped regions and wells, used in forming the sourceand drain regions of the transistors. Over the semiconductor layer 605,circuitry layers 670 are formed that contain chiplet-conductorsub-layers, such as a chiplet-conductor sub-layer for forming gateelectrodes and one or more chiplet-conductor sub-layers serving to formelectrical connections between the transistors. Circuitry layers 670include the connection pads, such as connection pads 353 b, 353 d, 354 aand 354 b formed in one of chiplet-conductor sub-layer.

The circuitry layers 670 and semiconductor layer 605 are furtherillustrated in the cross-sectional view of the chiplet 120 shown in FIG.7. The circuitry layers 670 also include several insulator sub-layerssuch as a gate insulator sub-insulator 124 and interlayer insulatorsub-layers 123, 122, and 121. These insulator sub-layers can beconstructed of materials such as silicon dioxide or other knowninsulator materials. The chiplet also includes a plurality ofchiplet-conductor layers. The first chiplet-conductor layer is arrangedto form gate electrodes, such as a gate electrode 127. Doped regions insemiconductor layer 605, such as a doped region 606 d, form source anddrain regions of transistors corresponding to the gate electrodes. Asecond chiplet conductor layer is provided for forming connectionsbetween transistors, such as the pass-thru connection 314 a. Theconnection pads, such as connection pads 351 a and 352 a, may be formedin a third chiplet-conductor layer. This configuration permits efficientlayout of the wiring in the second chiplet-conductor layer whilepermitting dense packing of connection pads in the thirdchiplet-conductor layer. However, in other embodiments, fewer or morechiplet-conductor layers can be employed. The thickness of the circuitrylayers 670 may depend on the number of chiplet-conductor sub-layers, andmay be between about 1 micrometer and about 15 micrometers. The totalthickness of the chiplet (H) includes a combination of the thickness ofthe semiconductor layer 605 and the circuitry layers 670, and may beless than 20 micrometers in some embodiments.

Turning back to FIGS. 6A and 6B, trenches, such as trench 640, areformed around each chiplet, such as chiplet 120. These trenches areetched through the semiconductor layer 605, exposing the buried oxidelayer. Anchor areas, such as anchor area 620, are provided betweenchiplets. The chiplets are attached to the anchor areas by smallmicro-bridges, such as micro-bridge 610, as described in U.S. patentapplication Ser. No. 11/421,654. Prior to forming the trenches, aprotection layer (not shown) of a material such as a photo-resist orsilicon nitride layer is formed over the integrated circuitry asdescribed in U.S. Patent Application Publication No. 2008/0108171. Arelease etch is then performed using an etchant such as hydrofluoricacid (HF) to remove the portion of the buried oxide layer disposed underthe chiplet and micro-bridges, leaving buried oxide portions 630 underthe anchors. In some embodiments, the release etch may be performed asdescribed in U.S. patent application Ser. No. 12/732,868, the disclosureof which is incorporated by reference herein. The protection layer canthen removed, exposing the chiplet connection pads. Chiplet 120 has awidth (W) and length (L) (as shown in FIG. 5). The anchor area 620 has awidth (I) that is greater than W in some embodiments to permit theburied oxide to be completely removed from under the chiplet while notcompletely etching the buried oxide under the anchor, so as to definethe buried oxide portions 630.

Turning back to FIG. 4 with elements additionally referenced from FIGS.2A and 5, adhesion layer 111 is applied to the display substrate 100 instep 530. The adhesion layer may be BCB or other common photo-resistmaterials as described above. The adhesion layer 111 may bephotosensitive.

The chiplets are picked up in step 540 with a stamp, for example, asdescribed in U.S. patent application Ser. No. 11/145,574. The stamp maybe constructed of a conformable material, such as poly(dimethylsiloxane) (PDMS), that has its undersurface formed into posts. Anexample stamp 800 is shown in FIG. 8. Stamp 800 includes a variety ofraised posts, such as post 810. The spacing of the posts ispredetermined to be a geometric multiple (integer or integer ratio) ofthe spacing of the chiplets on the integrated circuit substrate as wellas the pixels spacing on the display substrate. For example, thealignment of the stamp to the chiplets to the integrated circuitsubstrate is shown in FIG. 9, where the posts correspond to every secondchiplet (such as chiplet 120) in the

x-direction and every fourth chiplet in the y-direction. The posts onthe stamp pad can pick up a portion of the chiplets simultaneously inone stamping operation. Multiple stamping operations can then be used topopulate the entire display substrate with chiplets. This has theadvantage that, due to the area of high utilization efficiency of theintegrated circuit substrate area, the integrated circuit substrate areacan be much smaller than the area of the display.

In the pickup operation, the stamp is aligned so the posts 810 arelocated over the chiplets 120. The chiplets are then quickly detachedfrom the silicon on insulator substrate. As described in U.S. patentapplication Ser. No. 11/423,192, kinetic control of the adhesion forcesbetween the stamp and the chiplets enable the controlled fracture of thesupporting micro-bridges 610. The van der Waal's force between the stampand the chiplet causes the chiplets to remain in contact with the stampafter the micro-bridges are broken. This method of picking up thechiplets enables the chiplets to be very small in area. For example, achiplet with length or width dimensions of about 50 micrometers or lesscan be picked up using this method. Such dimensions are difficult toachieve using a vacuum suction apparatus, as the vacuum suction openingmust be smaller than the chiplet dimension. This technique also permitslarge arrays of such chiplets to be simultaneously transferred whilemaintaining good dimensional spacing and alignment between the chiplets.

In step 550, the stamp with the chiplets is aligned to the targetalignment marks 130 on the display substrate 100 and lowered so thechiplets 120 are in contact with the adhesion layer 111, therebyprinting the chiplets 120 onto the display substrate 100 in parallel. Inother words, multiple chiplets 120 are transferred to the displaysubstrate 100 substantially simultaneously. The bond with the adhesiveis stronger than the van de Waal's force so the chiplets remain on thedisplay substrate. The stamp is then withdrawn, leaving the chipletsadhered to the display substrate. The adhesive can then be cured.Optionally, the adhesive can also be removed in areas not under thechiplet. At this stage the chiplets are effectively mounted to thedisplay substrate.

In step 560, the planarization layer 112 is applied to the substrate,covering the chiplets. The BCB layer may be greater in thickness thanthe chiplets, which may be beneficial in reducing overall topography(variations in surface height) on the display substrate. Theplanarization layer is patterned to open the vias, such as via 143 aover the chiplet as described above. In some embodiments, theplanarizing material is itself a photo resist material, such asphotoimagable BCB, that can also be used as a mask to permit etching ofthe insulating sub-layer 121 on the chiplet 120 in order to expose themetal connection pads, such as connection pad 353 a in the chiplet. Atthis stage, the chiplet is effectively embedded in the display device.

In step 570, a conductor layer is deposited over top of theplanarization layer, and the metal layer is patterned to form wires.Standard photolithography methods and etching can be used to pattern thewires. Alternatively, the metal layer can be deposited in a pattern-wisefashion using methods such as ink-jet deposition of silvernano-particles.

In the case of a bottom emission OLED display, a transparent lowerelectrode 161 a is used. One approach to forming such a patternedelectrode is to deposit another insulator layer 113 of photoresist andto open vias therein for connection to the underlying metal layer, e.g.153 a. The transparent lower electrode 161 a is then deposited, forexample by sputtering, using a common transparent conductive oxide suchas ITO or IZO. This may be patterned using standard etching methods.Alternative transparent electrode materials may be used includingconductive polymeric materials such as PDOT/PSS copolymers. In analternative embodiment of a top-emission display, the patternedconductor layer could be used to form the reflective lower electrodes,eliminating the need for a separate conductor layer and interlayerinsulator layer 113.

The emission areas of each pixel are defined by openings 163 a ininsulator layer 114 that can be formed of a photo-imagable material.

In step 580, the electro-luminescent (EL) media 165 is formed. In someembodiments these are small molecule materials and a typical EL stackcontains layers for hole injection, hole transport, recombination andlight emission, electron transport and electron injection. Multiple ELstacks can also be used with connecting layers. One method of formingthe organic electro-luminescent media layers is by evaporation from acrucible or linear evaporation source. Alternatively these materials canbe polymeric and deposited by methods known in the art such a spincoating or inkjet coating.

In step 590, the upper electrode 169 is formed. In some embodiments thiselectrode is not patterned in the pixel area, but rather is continuousand electrically common across all the pixels. The upper electrode canbe deposited by evaporation or sputtering. For a bottom-emittingconfiguration, materials may include aluminum, a stack of aluminum overlithium or lithium fluoride, or magnesium silver alloys. In an alternatetop emitting embodiment, the upper electrode can be made to betransparent using materials such as transparent conductive oxides (likeITO) or thin metals (such as less than 25 nm of aluminum or silver). Thecircuit in the chiplet serves to regulate the current flowing verticallythrough the OLED stack between lower electrode 161 a and upper electrode169, producing the light emission 50 at desired intensities.

FIG. 5 shows a plan view of the chiplets 120 on the mother wafer, alsoreferred to herein as a source wafer, prior to pickup in step 540. Afteretching to release the chiplets in step 520, the chiplets remainattached by micro-bridges 610. The rows of chiplets are separated by theanchor area 620 that remain attached to the substrate below the etchedlayer. A cross section of the chiplet through Y-Y′ in FIG. 5 is shown inFIG. 6A and a cross section through Z-Z′ is shown in FIG. 6B. The buriedoxide portion 630 is completely removed from under the chiplet 120 butpartially remains under the anchor area. The micro-bridges 610mechanically support the chiplet after the etching is complete.

As previously described and further illustrated in FIG. 5, each chiplethas connection pads arranged in two rows including connection pads 351a, 351 b, 353 a, 353 b, 354 a, 355 a and 356 a arranged in a first rowand connection pads 352 a, 352 b, 353 c, 353 d, 354 b, 355 b and 356 barranged in a second row. The rows are arranged parallel to the length(L) direction. It is desirable that the width (W) be made small in orderto facilitate the release etch. Therefore the chiplet may be constructedwith either one or two rows of vias. The transistor and wiring circuitrywithin the chiplet can be fabricated using currently availablesemiconductor patterning technology. For example, semiconductorfabrication facilities can process feature sizes of about 0.5micrometers, about 0.35 micrometers, about 0.1 micrometers, about 0.09micrometers, about 0.065 micrometers, or smaller. The size of the pads,however, may be determined by the alignment and feature sizes of themetallization layers formed on the display substrate, and may berelatively large. For example, line, space, and via sizes of about 5micrometers with alignment accuracies of +/−5 micrometers would becompatible with chiplet connection pads that are 15 micrometers on aside (S) and spaced at 20 micrometers in pitch (P). Therefore, in someembodiments of the invention, the overall size of the chiplet may bedominated by the size and arrangement of the connection pads. It isdesirable that the size of the chiplet be made small so that manychiplets can be made simultaneously on the same integrated circuitsubstrate.

The connections to the chiplets made on the display substrate are shownin FIG. 1. It is desirable that the surface area of the displaysubstrate covered by the chiplet and the wiring be made small so thatthe surface area of the pixels available for emission is large. In orderto facilitate the connections to the chiplet while keeping the surfacearea of the wiring small, the arrangement of the connection pads on thechiplets is specifically selected. For example, the connection padsassociated with the select line segments (137 a, 137 b, 138 a, 138 b)are arranged at the ends (first and last) of each row of connectionspads. This may avoid the need to bend the select line segments, whichcan then be made small.

The data lines 135 and 136 are routed in a direction perpendicular tothat of the select lines segments. In the arrangement shown in FIG. 1,the data lines pass over the chiplet 120 in a continuous fashion. Assuch, it is desirable that the chiplet 120 be arranged so that itsshorter width (W) dimension is aligned parallel to direction of the datalines. The longer length (L) direction is therefore aligned parallel tothe select lines. The power line 131 is also routed in a continuousfashion in a direction perpendicular to that of the select linessegments and parallel to the shorter width (W) dimension of the chiplet120. These layout arrangements result in a large portion of the area ofthe chiplet under the signal lines being that of the connection pads,and reduce wasted non-connection pad areas covered by the signal linesso that the chiplet can be made small and the surface area of thedisplay substrate covered by the chiplets can also be made small. Insome embodiments, the power line may be arranged so as to be centeredover the chiplet as shown to simplify wiring to the pixels on each sideof the power line.

A pixel drive circuit of an alternate embodiment useful for protectingagainst electrostatic damage is shown in FIG. 10. Multiple pixel drivecircuits can be included on the chiplet to drive multiple pixels. Thepixel drive circuit includes a drive transistor 340 a, a selecttransistor 320 a, a storage capacitor 330 a and a diode 321 forelectrostatic discharge (ESD) protection. In the configuration shown,all the transistors are p-MOS, and only a single power connection pad356 a is used. If CMOS transistors are used, then another powerconnection may be required, which may add additional wiring in thepanel. The power connection pad 356 a is connected to the doped wellregions of the semiconductor bulk corresponding to transistors 320 a and340 a and also to the semiconductor bulk of the chiplet throughconnections 322. The ESD diode 321 is connected to connection pad 351 aand power connection pad 356 a. It provides protection for the gate ofselect transistor 320 a from voltage transients in manufacturing of thechiplet, during printing of the chiplet, during manufacturing of thedisplay and during operation. Although the methods of the presentinvention have been described above with respect to OLED devices,devices made according to embodiments of the present invention are notlimited thereto.

As discussed above, the process described and illustrated in FIG. 4 canfail. For example, the chiplets may include a material on the chipletsurface that prevents good adhesion with the stamp, the chiplets may notbe completely released from the wafer, and/or chiplets may be lostbetween pick up and placement on the substrate. Moreover, chiplets maybe misplaced or misaligned on the substrate, either in location ororientation, due to mechanical disturbances and/or tolerances in theprinting process. After the chiplets are printed, the process ofinterconnecting the chiplets, typically using conventional coating andphotolithographic processes, can fail, as such photolithographicprocesses may not have perfect yields.

Referring to FIG. 11, a method of assembling integrated circuit elementson a receiving substrate according to some embodiments of the presentinvention is illustrated in a flow chart that incorporates the stepsillustrated in FIG. 4 and serves to correct some or all of thedeficiencies of the processes described above. According to someembodiments of the present invention, a method of making a large-formatsubstrate with distributed integrated circuit control elementssequentially providing a substrate at step 900 and providing a wafer atstep 905, the wafer having a plurality of separate, independent chipletsformed thereon; the chiplets formed, for example, by steps 510 and 520of FIG. 4. The wafer is imaged at step 910 and the wafer image analyzedat step 920 to determine 930 which of the wafer chiplets are defective.The defective chiplet(s) are removed from the wafer at step 940, leavingremaining chiplets in place on the wafer. The defective chiplet(s) canbe removed from the wafer by printing defective chiplet(s) onto adifferent adhesive substrate, for example, by the same process as isused to print onto the display substrate, or by using a differentremoval process. The remaining chiplet(s) are printed onto the substrateat step 950, for example, by steps 540 and 550 of FIG. 4, forming emptychiplet location(s) on the substrate. All of the remaining chiplets maybe printed onto the substrate in parallel, e.g., substantiallysimultaneously in a parallel transfer printing operation. The additionalchiplet(s) (also referred to herein as “missing” chiplets) are thenprinted at step 970, from the same or a different wafer, into the emptychiplet location(s) on the substrate. The substrate then is completelypopulated with chiplets and there are no missing chiplets or emptychiplet locations.

The chiplets printed are likely to be working chiplets, since theprocess of imaging at step 910 and analysis at step 920 of the chipletscan detect faulty chiplets so that only working chiplets are printed atstep 950 onto the substrate. However, to further improve the likelihoodof successful manufacture and to overcome any faults in the printingprocess itself, the substrate can be imaged at step 952 after theremaining chiplet(s) are printed at step 950 and the substrate imageanalyzed at step 954 to determine the empty chiplet location(s). Thisanalysis at step 954 can be done in addition to the analysis of thewafer image at step 920.

In addition to detecting missing chiplets, the image of the printedchiplets can be used to detect mis-located chiplets at step 956.Alignment marks 130 a and 130 b can be used to determine with highprecision (typically less than about 1 micrometer) the location andorientation of each chiplet. As used herein, a mis-located chiplet isone whose location on the substrate is not as desired or whose rotationor orientation on the substrate is not as desired or is otherwisemisaligned relative to other chiplets. Furthermore, the image of theprinted chiplets can be employed to detect faulty printed chiplets atstep 958. This is useful for example, if the chiplets have been damagedin printing and/or as a second part of the faulty chiplet analysis instep 930.

Once detected, faulty or mis-located printed chiplets can be removedfrom the substrate at step 960. The chiplets can be lightly adhered tothe substrate after printing, and the adhesive can be cured to form amore permanent adhesion. Hence, the chiplet can be removed beforeadhesive curing. For example, according to some embodiments of thepresent invention, a rework stamp having a single transfer post and anarray of anti-sag features can be laminated onto the defective chiplet.The shape, profile and printing process parameters can be adjusted usingflowing methods disclosed in U.S. patent application Ser. No. 11/423,192filed Jun. 9, 2006 titled “PATTERN TRANSFER PRINTING BY KINETIC CONTROLOF ADHESION TO AN ELASTOMERIC STAMP.” and U.S. Pat. App. No. 61/116,136filed Nov. 19, 2008 titled “PRINTING SEMICONDUCTOR ELEMENTS BYSHEAR-ASSISTED ELASTOMERIC STAMP TRANSFER” to insure successfulretrieval of the chiplet from the substrate. Alternatively, an element(for example, a metal cylinder) having a substantially flat surface withholes can be located on the chiplet, the cylinder can be evacuated andthe chiplet can be adhered to the flat surface by air pressure. Thecylinder and chiplet can then mechanically remove the chiplet from thesubstrate. As another alternative, a mechanical device having small jawscan grasp the chiplet and mechanically remove it. Since the chipletsthemselves are in the tens of microns in size, other methods in themechanical arts can accomplish this removal at step 960. Once removed toform an empty chiplet location on the substrate, a chiplet can beprinted into the empty chiplet location at step 970.

In further embodiments of the present invention, the chiplets on thewafer can be electrically tested at step 922, for example, by providingwires that connect to the chiplets formed on the wafer and employingcircuitry on the wafer, or external to the wafer, to electricallystimulate the chiplets and test the chiplets' functionality. Thosechiplets that fail the functional test can be determined to bedefective, even without any visible, imaged faults. The tests can bedone before or after release of the chiplets from the wafer. If doneafter release, the micro-bridges connecting the chiplets to the wafercan incorporate electrical connections. These electrical connections canbe formed using selectively-doped silicon micro-bridges, poly-silicon ormetal lines or any combination of the above. Serial first-in-first-outstorage registers can be employed or addressing circuitry, together withserial or parallel registers for applying signals to the chiplets andrecording signals from the chiplets to determine functionality. Theelectrical test can be done in addition to or as an alternative to theimaging test.

As described above, once a substrate is fully populated with operativechiplets, the substrate and chiplets can be processed to electricallyinterconnect the chiplet(s) with wires formed over the substrate.Organic electro-luminescent structures (e.g. OLEDs) that are operableresponsive to signals provided by the chiplets can then be formed overthe substrate at step 1040. The wires are employed to drive the circuitsand operate the device. Unfortunately, the processes used to process thesubstrate and chiplets to form the electrically-interconnecting wirescan fail so that the chiplets are not properly interconnected. Infurther embodiments of the present invention, the substrate can beimaged at step 980 to determine faulty interconnected chiplet(s), and/oran electrical test of the substrate and chiplet(s) can be performed atstep 982 after the chiplet(s) are electrically interconnected todetermine faulty interconnected chiplet(s).

Once the faulty interconnected chiplets are determined, the faultyinterconnected chiplets may be removed at step 990 to form empty chipletlocations. The removal can be accomplished by removing material adheredto and surrounding the chiplet(s) and then removing the chiplet(s) toform empty chiplet location(s). For example, laser ablation or localchemical processing can be used to separate a faulty interconnectedchiplet from the substrate and surrounding material. A photolithographicprocess comprising coating a photosensitive resin over the substrate andpattern-wise exposing and processing the photosensitive resin to form alocally chemically processable area over and around the chiplet(s) canbe employed. Once removed, the missing chiplet(s) may be printed at step1000 into the empty chiplet location(s) and then electricalinterconnection(s) to the printed missing chiplet(s) may be formed atstep 1010. Photolithographic processes can be employed, for example byfirst protecting the operative portions of the substrate, and thenprocessing the substrate as before to form the local connections, andthen removing remaining materials from the operative substrate areas.

In some embodiments of the present invention, rather than removingfaulty interconnected chiplet(s), the faulty interconnected chiplet(s)can be buried at step 1020 under a planarization layer after firstcutting any existing electrical connections, for example with a laser.Once the faulty interconnected chiplet(s) are buried, a second chipletcan be printed at step 1030 over one or more of the faultyinterconnected chiplet(s) and then electrical interconnection(s) to thesecond chiplet can be formed.

In other embodiments of the present invention, to further enable theremoval of defective or mis-located chiplets, a photosensitive adhesivecan be coated over the substrate to adhere the printed chiplet(s) to thesubstrate. The adhesive can be negatively or positively exposed in thelocations of defective or mis-located chiplet(s) to reduce the adhesionbetween the defective or mis-located chiplet(s) and the substrate. Thus,removal of the defective or mis-located chiplets may be facilitated.

The methods of the present invention can be employed to form an OLEDdevice on the substrate at step 1040 to be controlled by the printedchiplet(s).

The flowcharts described above illustrate the architecture,functionality, and operations of embodiments of hardware and/or softwareaccording to various embodiments of the present invention. It will beunderstood that each block of the flowchart and/or block diagramillustrations, and combinations of blocks in the flowchart and/or blockdiagram illustrations, may be implemented by computer programinstructions and/or hardware operations. In this regard, each blockrepresents a module, segment, or portion of code, which comprises one ormore executable instructions for implementing the specified logicalfunction(s). It should be noted that, in other implementations, thefunction(s) noted in the blocks may occur out of the order noted inFIGS. 4 and 11. For example, two blocks shown in succession may, infact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending on thefunctionality involved.

The computer program instructions may be provided to a processor of ageneral purpose computer, a special purpose computer, or otherprogrammable data processing apparatus to produce a machine, such thatthe instructions, which execute via the processor of the computer orother programmable data processing apparatus, create means forimplementing the functions specified in the flowchart and/or blockdiagram block or blocks. The computer program instructions may also bestored in a computer usable or computer-readable memory that may directa computer or other programmable data processing apparatus to functionin a particular manner, such that the instructions stored in thecomputer usable or computer-readable memory produce an article ofmanufacture including instructions that implement the function specifiedin the flowchart and/or block diagram block or blocks.

Accordingly, embodiments of the present invention may provide advantagessuch that, by providing a process having examination, test, andreplacement operations at various stages of assembly, the overall yieldof substrates may be improved.

The invention has been described in detail with particular reference tocertain preferred embodiments thereof, but it should be understood thatvariations and modifications could be effected within the spirit andscope of the invention.

1. (canceled)
 2. A wafer of chiplets, the wafer comprising: a sourcesubstrate having an array of regularly-spaced chiplet locations thereon;and a plurality of chiplets native to the source substrate, each chipletof the plurality of chiplets disposed on the source substrate in one ofthe chiplet locations in the array, wherein one or more of the chipletlocations in the array is a removed-chiplet location that is devoid of achiplet.
 3. The wafer of claim 2, wherein each chiplet of the pluralityof chiplets is partially released from the substrate such that eachchiplet is connected to the substrate via a micro-bridge of a pluralityof micro-bridges.
 4. The wafer of claim 2, wherein each chiplet isconnected to the substrate via a micro-bridge of a plurality ofmicro-bridges.
 5. The wafer of claim 4, wherein each micro-bridgesupports a respective chiplet.
 6. The wafer of claim 4, comprising aplurality of anchors on the source substrate, wherein each micro-bridgeis connected to an anchor of the plurality of anchors.
 7. The wafer ofclaim 6, comprising a buried oxide layer under the plurality of anchors.8. The wafer of claim 7, wherein the buried oxide layer is under thechiplet.
 9. The wafer of claim 4, wherein the plurality of micro-bridgesconnecting the chiplets to the wafer comprise electrical connections.10. The wafer of claim 9, wherein the micro-bridges compriseselectively-doped semiconductor material, thereby providing theelectrical connections.
 11. The wafer of claim 9, wherein the electricalconnections comprise metal lines.
 12. The wafer of claim 2, comprisingwires connected to the plurality of chiplets.
 13. The wafer of claim 2,comprising electrical connections to each chiplet of the plurality ofchiplets.
 14. The wafer of claim 2, comprising test circuitry forelectrically stimulating the plurality of chiplets to test chipletfunctionality.
 15. The wafer of claim 2, comprising one or more storagedevices for recording signals from the chiplets to determinefunctionality.
 16. The wafer of claim 15, wherein the one or morestorage devices are one or more storage registers.
 17. The wafer ofclaim 2, wherein the chiplets are organic light emitting diodes.
 18. Thewafer of claim 2, wherein the chiplets are independent control elements.19. The wafer of claim 2, wherein the chiplets have a thickness of lessthan 20 micrometers.
 20. The wafer of claim 2, wherein the chiplets areconfigured to control organic light emitting diodes.
 21. The wafer ofclaim 2, wherein the chiplets are arranged to control electrical currentto pixels.